The present invention relates to level shift circuits used as interfaces between circuits with different power source voltages.
As processing has become increasingly miniaturized in recent years, there has been a tendency toward reducing the power source voltage of circuits in semiconductor integrated circuits for the sake of element reliability. On the other hand, the same conventional power source voltage continues to be used for some of the elements employed in systems such as electrical appliances. An interface is generally established between elements and semiconductor integrated circuits with different power source voltages by providing a level shift circuit within the semiconductor integrated circuits.
Also, in some recent semiconductor integrated circuits, an optimal power source voltage is supplied to each circuit block to reduce power consumption, and level shift circuits are also used to establish an interface between these circuit blocks with different power source voltages. It is likely that the need for such level shift circuits will continue to increase in the future.
An example of a conventional level shift circuit is shown in FIG. 13. In FIG. 13, numerals 1 and 2 denote n-channel transistors, 3 and 4 denote p-channel transistors, VDD denotes a high voltage power source, VSS denotes a ground power source, IN denotes an input signal, XIN denotes an inverted input signal, OUT denotes an output signal, and XOUT denotes an inverted output signal. For the n-channel transistors 1 and 2, at their gate electrodes are input the input signal IN and the inverted input signal XIN, respectively, and their source electrodes are connected to the ground power source VSS. The drain electrodes of the p-channel transistors 3 and 4 are connected to the drain electrodes of the n-channel transistors 1 and 2, and their source electrodes are connected to the high voltage power source VDD. The p-channel transistors 3 and 4 are connected in a cross-coupled arrangement, in which the gate electrode of one is connected to the drain electrode of the other. The inverted output signal XOUT is output from the point where the p-channel transistor 3 and the n-channel transistor 1 are connected, and the output signal OUT is output from the point where the p-channel transistor 4 and the n-channel transistor 2 are connected.
Next, the operation of this conventional level shift circuit is described. As one example, the operation will be described with an amplitude level of the input signal IN and the inverted input signal XIN at 1.5 V, a power source potential of the high voltage power source VDD at 3 V, the potential of the ground power source VSS at 0 V, and an amplitude level of the output signal OUT and the inverted output signal XOUT at 3 V.
First, as the initial state, the input signal IN is set to 0 V, the inverted input signal XIN is set to 1.5 V, the output signal OUT is set to 0 V, and the inverted output signal XOUT is set to 3 V At this time, the n-channel transistor 1 and the p-channel transistor 4 are in a non-conducting state and the n-channel transistor 2 and the p-channel transistor 3 are in a conducting state.
Next, let us consider a case in which the input signal IN is changed to 1.5 V and the inverted input signal XIN is changed to 0 V Due to this change, the n-channel transistor 1 is shifted into a conducting state and the n-channel transistor 2 is shifted into a non-conducting state. At this time, because the p-channel transistor 3 is in a conducting state, the potential of the inverted output signal XOUT drops to an intermediate value determined by the ratio of the conduction resistances of the n-channel transistor 1 and the p-channel transistor 3. When this intermediate value exceeds the threshold voltage of the p-channel transistor 4, the p-channel transistor 4 is shifted into a conducting state and the potential of the output signal OUT is stepped up. When the potential of the output signal OUT is stepped up, the p-channel transistor 3 is shifted to a non-conducting state, and as a result the conduction resistance of the p-channel transistor 3 is increased and the potential of the inverted output signal XOUT is dropped further.
With the above-described positive feedback, the operation for changing the output signal OUT to 3 V and the inverted output signal XOUT to 0 V and thereby shifting the input signal, which has a low amplitude level, to an output signal that has a large amplitude level is completed. Thus, for example, a signal with a low power source voltage level inside a semiconductor integrated circuit can be shifted to an outside signal with a high power source voltage level.
However, with conventional level shift circuits, it was found that the following problem becomes noticeable when the power source voltage is reduced. That is, in the level shift circuit shown in FIG. 13, high withstand voltage transistors with a thick gate oxide film able to withstand high voltages are used for the n-channel transistors 1 and 2, and these high voltage resistance transistors generally have a large threshold voltage (for example, 0.5 V). Thus, when the voltage levels of the input signal IN and the inverted input signal XIN have dropped to near the threshold voltage of the n-channel transistors 1 and 2 (for example, to 0.7 V), the n-channel transistors 1 and 2, into whose gate electrodes the signals IN and XIN are input, experience a very rapid decline in performance. As a result, when the signals IN and XIN are changed from 0 V to a predetermined voltage level (0.7 V), a problem that occurs is that the operation for shifting to the conducting state of the n-channel transistors 1 and 2 is slow, resulting in poorer overall operating speed of the level shift circuit.
As mentioned above, the recent progress in miniaturization has tended toward a reduction in the power source voltage inside semiconductor integrated circuits. Thus, how these low voltage level signals will be shifted to a high voltage level at high speeds becomes a crucial problem as progress in achieving progressively lower voltage levels continues.
It is an object of the present invention to achieve a level shift circuit for shifting an input signal with a low voltage level to an output signal with a high voltage level that performs this signal level shift at high speeds and low power, even if innovations continue to reduce the voltage level of the input signal.
To achieve the above object, the present invention utilizes the effects of transistor substrate biasing, so that in a transistor into which is input an input signal at its gate electrode, a positive voltage is applied to the substrate of the transistor only when the input signal changes as it rises to the power source voltage level, so as to lower the threshold voltage and achieve higher operating speeds for the transistor.
More specifically, a level shift circuit of the invention, into which an input signal and an inverted input signal are input, which shifts an amplitude level of the input signal and the inverted input signal to an amplitude level that is higher than that amplitude level, and which outputs at least one of an output signal and an inverted output signal having the amplitude level after shifting, and includes a first n-type transistor for signal input into whose gate electrode the input signal is input, a second n-type transistor for signal input into whose gate electrode the inverted input signal is input, a first p-type transistor for substrate bias, into whose source electrode the input signal is input, whose drain electrode is connected to a substrate of the first n-type transistor for signal input, and into whose gate electrode the output signal is input, and a second p-type transistor for substrate bias, into whose source electrode the inverted input signal is input, whose drain electrode is connected to a substrate of the second n-type transistor for signal input, and into whose gate electrode the inverted output signal input.
In another aspect of the invention, the level shift circuit further includes a first n-type transistor for resetting, whose source electrode is connected to a low voltage power source, whose drain electrode is connected to the substrate of the first n-type transistor for signal input, and into whose gate electrode the output signal is input, and a second n-type transistor for resetting, whose source electrode is connected to the low voltage power source, whose drain electrode is connected to the substrate of the second n-type transistor for signal input, and into whose gate electrode the inverted output signal is input.
In a further aspect of the invention, the level shift circuit includes a first delay element connected to the gate electrode of the first n-type transistor for resetting, and which is for delaying input of the output signal to that gate electrode, and a second delay element connected to the gate electrode of the second n-type transistor for resetting, and which is for delaying input of the inverted output signal to that gate electrode.
In a yet further aspect of the invention, in the level shift circuit, the inverted output signal and the output signal are input into the drain electrodes of the first and the second n-type transistors for signal input, respectively, and the level shift circuit further includes a p-type transistor for blocking, which is arranged on a route connecting a high voltage power source to the drain electrodes of the first and the second n-type transistors for signal input, into whose gate electrode a control signal is input and which becomes non-conducting when a power source of a circuit that outputs the input signal and the inverted input signal is shut down, and first and second n-type transistors for shutdown, arranged between the drain electrodes of the first and the second n-type transistors for signal input and the low voltage power source, respectively, into whose gate electrodes the control signal is input and which become conducting during the shut down.
In another aspect of the invention, in the level shift circuit, at least the first and the second n-type transistors for signal input are formed on an insulating substrate.
In an even further aspect of the invention, in the level shift circuit, a signal line is connected to the drain electrode of at least one of the first and the second n-type transistors for signal input, and through the signal line, only one of the output signal and the inverted output signal is output.
A further level shift circuit according to the invention, into which an input signal and an inverted input signal are input, which shifts an amplitude level of the input signal and the inverted input signal to an amplitude level that is higher than that amplitude level, and which outputs at least one of an output signal and an inverted output signal, which is the output signal inverted, having the amplitude level after shifting, and includes a first n-type transistor for signal input, into whose gate electrode the input signal is input, a second n-type transistor for signal input, into whose gate electrode the inverted input signal is input, a first n-type transistor for substrate bias, into whose source electrode the input signal is input, whose drain electrode is connected to a substrate of the first n-type transistor for signal input, and into whose gate electrode the inverted output signal is input, and a second n-type transistor for substrate bias, into whose source electrode the inverted input signal is input, whose drain electrode is connected to a substrate of the second n-type transistor for signal input, and into whose gate electrode the output signal is input.
In another aspect of the invention, the level shift circuit further includes a first n-type transistor for resetting, whose source electrode is connected to a low voltage power source, whose drain electrode is connected to the substrate of the first n-type transistor for signal input, and into whose gate electrode the output signal is input, and a second n-type transistor for resetting, whose source electrode is connected to the low voltage power source, whose drain electrode is connected to the substrate of the second n-type transistor for signal input, and into whose gate electrode the inverted output signal is input.
In a further aspect of the invention, the level shift circuit includes a first delay element connected to the gate electrode of the first n-type transistor for resetting, and which is for delaying input of the output signal to that gate electrode, and a second delay element connected to the gate electrode of the second n-type transistor for resetting, and which is for delaying input of the inverted output signal to that gate electrode.
In a yet further aspect of the invention, in the level shift circuit, the inverted output signal and the output signal are input into the drain electrodes of the first and the second n-type transistors for signal input, respectively, and the level shift circuit further includes a p-type transistor for blocking, which is arranged on a route connecting a high voltage power source to the drain electrodes of the first and the second n-type transistors for signal input, into whose gate electrode a control signal is input and which becomes non-conducting when a power source of a circuit that outputs the input signal and the inverted input signal is shut down, and first and second n-type transistors for shutdown, arranged between the drain electrodes of the first and the second n-type transistors for signal input and the low voltage power source, respectively, into whose gate electrodes the control signal is input and which become conducting during the shut down.
In another aspect of the invention, in the level shift circuit, at least the first and the second n-type transistors for signal input are formed on an insulating substrate.
In an even further aspect of the invention, in the level shift circuit, a signal line is connected to the drain electrode of at least one of the first and the second n-type transistors for signal input, and through the signal line, only one of the output signal and the inverted output signal is output.
Thus, with the invention, when the input signal or the inverted input signal rises toward a higher voltage level, that signal is also applied to the substrate of the first or the second n-type transistor for signal input into whose gate the signal is input. As a result, the threshold voltage of the first or the second n-type transistor for signal input is lowered due to the substrate bias effect, and thus can quickly operate in a conductive state, even if the input signal or the inverted input signal has been reduced to a low voltage level.
Moreover, after the input signal or the inverted input signal has risen to a high voltage level, the potential of the output signal or the inverted output signal become high voltage and the corresponding first or second p- or n-type transistor for substrate bias is shifted to a non-conducting state, so that these signals are prevented from being applied to the substrate of the first or the second n-type transistor for signal input, except for when the signals are rising and changing. Consequently, a constant flow of passing-through current can be prevented from flowing to the substrate of the first or the second n-type transistor for signal input, and this lowers power consumption.
In addition, with the invention, for example, when the output signal has risen to a high voltage level due to the rise in the input signal, this output signal causes the first n-type transistor for resetting to become conducting and the substrate of the first n-type transistor for signal input, into whose gate electrode the input signal is input, to be reset to the potential of the low voltage power source, thereby preparing for the next rise in the input signal. Thus, a history effect in the operations of the first n-type transistor for signal input is inhibited, thereby effectively inhibiting variation in the operation delay of the transistor.
Moreover, with the invention, the resetting operation of the first and the second n-type transistors for resetting is delayed by the corresponding first and second delay elements, and thus high-speed operation resulting from biasing the substrate of the first and the second n-type transistors for signal input is maintained until the change in the signals is complete.
In addition, with the invention, when the power source of the circuit supplying the input signal and the inverted input signal is shut down, the potential level of the input signal and the inverted input signal becomes unstable, and together with this the first and the second n-type transistors for signal input become conductive, which leads to the risk that passing-through current will flow within the level shift circuit, however, at this time, the p-type transistor for blocking becomes non-conductive and the first and the second n-type transistors for shut down become conducting, thereby blocking the passing-through current route from the high voltage power source of the level shift circuit to the first and the second n-type transistors for signal input, and thus the flow of passing-through current during shut down is prevented. Also, because the output signal and the inverted output signal are held constant at the ground potential, passing-through current can be kept from flowing to circuits in later stages.
In addition to this, with the invention the first and the second n-type transistors for signal input are formed on an insulating substrate, so that an isolation region for isolating the substrates of these transistors from one another becomes unnecessary, allowing the layout area to be reduced.